At present there are a number of standard integrated circuits having a plurality of components whose operations and functions are well documented in the manufacturer's manual and other publications. Sometimes, the operations are presented in a truth table which sets out the expected state of the output pins for any given states of the input pins. However, the information given may not always be accurate and complete especially as a manufacturer may not want to publicise all the functions of a chip, some vital information may be omitted by the writer of the manufacturer's manual and if the truth table is digitally encoded then there may not be all the information required to simulate the i.c.
On the other hand, application specific integrated circuits (ASICs) or custom chips often are not accompanied by documented information concerning their operations and functions. The minimum amount of information is usually only given such as the pin names, pin types (i.e. inputs, output etc.), pin ordering and so on. In order to learn from the ASICs or custom chips it is necessary to determine its various operations and functions. A known system for obtaining such functions using a known computer and memories is shown schematically in FIG. 1.
Various tests are made on the ASICs or custom chips by applying voltages or stimuli to the input pins and the changes in the state of the output pins are measured. The results of the tests and the basic information supplied by the manufacturer are then passed to an engineer, known as a modeler, to create a model of the ASICs using his experience. The model is written in a particular computer program language and stored on a compatible system. This model is first tested by the modeler who applies certain stimuli and compares the actual results with the expected results using a simulator. Modifications to the model are made if required. The model and stimulus and results are stored in a library. The operations and functions of the i.c. can be extracted from this stored information. Consequently, the library can be used in the development of the ASIC or by electrical engineers generating circuits using this ASIC.
The testing system may be either a digital simulator, or an analogue simulator. A digital simulator is one that is event driven such that when a stimulus, is applied, the simulator notes that it should schedule an output change after a given period of time T. At T the next stimulus is then applied.
An analogue simulator is not event driven. It applies a stimulus to an input pin and measures the voltage or current at an number of nodes in the ASIC model at equal intervals over a given time period. When testing the model using an analogue simulator it can take up to 10 to 20 hours to apply a particular type of stimulus to the model. If the ASIC is complex, any one of up to 9 types of stimulus may be required. Consequently, an analogue simulator is relatively slow, produces a far greater quantity of results but is more accurate than a digital simulator.
In any case, in order to fully analyse all the functions of the ASIC a large number of stimuli must be applied which generates an enormous set of results. Creating and testing the model in this way, especially using an analogue simulator is extremely labour intensive and time consuming.
The model is written in a particular computer language for use on a particular system. If the model is required on a non-complimentary system, then the modeler must rewrite the model in a suitable computer language. Consequently, ASIC foundaries often produce and support different systems containing the same libraries on the same ASIC. This is extremely time consuming and inefficient.
One further disadvantage known with this system of determining the operations of an ASIC is that the libraries are extremely memory intensive and consequently slow to use and extract information therefrom.
An aim of the present invention is to provide a system and processor for use therein which overcomes these disadvantages.
According to the present invention there is provided a system for determining the operations of an integrated circuit, comprising:
means for receiving and storing information about said i.c. and for storing a range of stimuli to be applied to a model of said i.c.;
means for selecting at least one stimulus;
a first translator for translating said selected stimulus from a reference language into an alien language;
an alien simulator for applying said stimulus to an alien model of said i.c. and obtaining a response to said stimulus;
a second translator for translating said stimulus and responses from said alien language to said reference language; and
store means for storing said stimulus and responses, said stimulus and responses representing the operations of the i.c.
The present invention thus provides a system using a known computer in conjunction with another computer housing an existing alien model (i.e. one that has already been generated by a modeler but in another language) and automatically generates a reference library from which other alien simulator libraries can be produced by extracting information from the reference library. The system is thus more efficient and quicker because only one model need be generated and the other simulators can be generated from the reference library.
Also according to the present invention there is provided a processor for condensing a truth table, comprising:
means for receiving said truth table;
means for executing the following three steps in order, or for executing only one of the three steps or for executing the first two steps in order or for executing the last two steps in order, said steps comprising
1) comparing two entries identical in all respects apart from the state of one pin to ascertain whether the state of said pin determines the output of the entries and if the state of said pin is independent of the output then for deleting one of said entries and for repeating the comparison for all input pins
2) identifying two or more entries where the state of the output pin is equal to the state of one of the input pins, the same input pin in each entry, for deleting one or all but one of those entries and amending the remaining entry by inserting the number of the input pin for the state of the output pin and
3) detecting which output state occurs most often, selecting those entries, deleting all but one of those entries and amending the remaining entry by inserting a neutral state for each input pin; and
means for outputting the condensed truth table.
This processor enables the results obtained to be condensed to a more manageable form so that the reference library is not memory intensive and the information can be extracted relatively quickly.